“IMAGE SCANNING DEVICE AND SELECTING CIRCUIT” disclosed in JP-A-2001-45383 (pages 2 to 5, FIGS. 1 to 11)(hereinafter referred to as Patent Document 1) has been known as an image scanning device having an image scanning element group constructed by arranging image scanning elements in a matrix form. This type of image scanning device is designed so that pixel portions (image scanning elements) arranged in a matrix form to constitute an image scanning element group are sequentially scanned by a horizontal shift register portion for selecting the image scanning elements for every column and a vertical shift register portion for selecting the image scanning elements every line to thereby take out a pixel signal from each pixel portion. In order to solve problems such as an increase of the scale of the peripheral circuits and increase of the scanning time in connection with increase of the number of the image scanning elements, that is, the number of pixels, there has been proposed an image scanning device having the construction that the sensor portion is divided into plural selection blocks and the scanning is carried out every selection block.
Furthermore, there is also known an image scanning device using a CMOS type as an image scanning device (CMOS image sensor), and for example, there is known “SOLID-STATE IMAGE SCANNING DEVICE” disclosed in JP-A-11-196332 (pages 2 to 6, FIGS. 1 to 9)(hereinafter referred to as Patent Document 2).
However, this image scanning device has problems in pixel signal take-in speed, current consumption, etc., and thus a mechanism of reading a necessary range of pixel signals on a block basis to solve the above problem has been proposed.
According to the techniques disclosed in the above documents, plural image scanning elements are blocked every predetermined range, and scanning or skip reading is carried out for every block, thereby achieving high-speed reading in spite of reduction in resolution.
However, according to the “IMAGE SCANNING DEVICE AND SELECTING CIRCUIT” disclosed in the Patent Document 1, the pixel portions can be scanned on a selection block basis (patent Document 1; FIGS. 2, 3), however, the pixel signals in each selection block are successively read out and outputted to the external (Patent Document 1; FIG. 4). Therefore, in order to process these pixel signals, it is necessary that after the pixel signals are subjected to A/D conversion, they are temporarily stored in a memory device or the like and then the output values of any pixels are summed and processed. Therefore, not only the signal processing is cumbersome, but also the memory device as described above and the peripheral circuits thereof are indispensable. In the Patent Document 1, a DRAM memory is used as a temporary storage area to execute image processing, and data stored in this memory are processed by MPU or camera DSP. Accordingly, there is a problem that it is difficult to simplify the output processing of the device concerned, and enhancement of the processing is disturbed. Furthermore, the memory device or the like is required to be provided at the outside of the image scanning device concerned, so that the scale of the system is increased as a whole and also the cost of products is increased.
Furthermore, no specific construction is disclosed in the “SOLID-STATE IMAGE SCANNING DEVICE” disclosed in the Patent Document 2. However, as in the case of the Patent Document 1, after A/D conversion is carried out, it is necessary to store pixel data into a memory device or the like before digital signal processing. Therefore, it is estimated that a memory device as described above and peripheral circuits therefore are indispensable to this technique, and thus this technique has also the same problems as described above. Furthermore, even when such a memory device and a CMOS type image scanning device can be formed on the same semiconductor substrate by a CMOS manufacturing process, the mount area of the memory device, etc. is required on the semiconductor substrate, and thus the chip size may be increased in connection with increase of the storage capacity, and also the manufacturing cost may be further increased in accordance with the scale of the memory device and the peripheral circuits therefore.
On the other hand, in a case where the image scanning device is designed so that all pixel signals output from the respective image scanning elements after A/D conversion are subjected to signal processing by MPU or DSP without using any memory device, all the pixel signals of the respective image scanning elements are read out, and then a necessary range of pixel signals are read out every block on the basis of the signal processing result and subjected to signal processing again. Therefore, twice or more reading operation is forcedly required to the memory device, so that the processing speed of MPU or the like is lowered. Furthermore, when the high-speed operation is required, the reading frequency to the image scanning elements is increased, which causes increase of the processing time and thus it is difficult to satisfy the requirement concerned. On the other hand, the above-described problems can be solved by utilizing as a memory device, MPU or the like a semiconductor device that can shorten the memory access time. However, it induces such a new problem that power consumption and heating value are increased due to the high speed operation.